library verilog;
use verilog.vl_types.all;
entity cortex_m0 is
    generic(
        BE              : integer := 0;
        BKPT            : integer := 4;
        DBG             : integer := 1;
        NUMIRQ          : integer := 32;
        SMUL            : integer := 0;
        SYST            : integer := 1;
        WIC             : integer := 0;
        WICLINES        : integer := 34;
        WPT             : integer := 2
    );
    port(
        XTAL1           : in     vl_logic;
        XTAL2           : out    vl_logic;
        NRST            : in     vl_logic;
        nTRST           : in     vl_logic;
        TDI             : in     vl_logic;
        TDO             : out    vl_logic;
        SWDIOTMS        : inout  vl_logic;
        SWCLKTCK        : in     vl_logic;
        uart0_RX        : inout  vl_logic;
        uart0_TX        : inout  vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of BE : constant is 1;
    attribute mti_svvh_generic_type of BKPT : constant is 1;
    attribute mti_svvh_generic_type of DBG : constant is 1;
    attribute mti_svvh_generic_type of NUMIRQ : constant is 1;
    attribute mti_svvh_generic_type of SMUL : constant is 1;
    attribute mti_svvh_generic_type of SYST : constant is 1;
    attribute mti_svvh_generic_type of WIC : constant is 1;
    attribute mti_svvh_generic_type of WICLINES : constant is 1;
    attribute mti_svvh_generic_type of WPT : constant is 1;
end cortex_m0;
